COE/EE 243 Lect #40 Lecture given by Jim Frenzel. The notes below are what I had scheduled to cover, with input from Jim on what was presented. MSI Counters: Most popular MSI counter is the 74x163 synchronous counter. All flip-flops clock inputs connected to a common clock. It has a synchronous load and synchronous clear. Uses 4 D flip flops Inputs Current State Next State /CLR /LD ENT ENP Qd Qc Qb Qa Qd* Qc* Qb* Qa* ---------------- ----------- --------------- 0 X X X X X X X 0 0 0 0 Clear 1 0 X X X X X X D C B A Parallel Load 1 1 0 X X X X X Qd Qc Qb Qa No change 1 1 X 0 X X X X Qd Qc Qb Qa No change 1 1 1 1 Count (Count + 1) Mod 16 Increment count Ripple Carry Out or RCO is carry from the MSB and is 1 only if Count = 15 and ENT = 1. CLR, etc are also synchronized with the clock. Use the inputs and Load Enable to vary the count sequence Example Qd Qc Qb Qa | | | | ___|_____|_____|_____|___ | |-----+---- P=T=1 CLK-------o|> |_____| _______| 74x163 | | Carry| |o---- CLR=1 _|_ | Dd Dc Db Da |o----+ LD \ / |________________________| | V | | | | | o | | | | | | 0 1 1 1 | |_____________________________________| We are inputing a 7 whenever LD = 0, which will be the case when count reaches 15 (1111) and we get the RCA (carry) = 1 So the count goes: 7-8-9-10-11-12-13-14-15-7-8-9-.... Or we can use the outputs and clear to vary it as well. _____ ________________________| \ | ______| \ | | NAND )o--------+ | ______| / | | | | |_____/ | ___|_____|_____|_____|___ | | Qd Qc Qb Qa |-----+---- P=T=1 | CLK-------o|> |_____| | ____| 74x163 | | Carry | |o-------------------+ | Dd Dc Db Da |o---- LD |________________________| | | | | | | | | Now we force a clear whenever the count reaches 1001, so the counter counts the sequence: 0,1,2,3,4,5,6,7,8,9,0,1,2,3 The count can also be varied by using the outputs and clear as well. _____ ________________________| \ | ____________| \ | | | NAND )o--------+ | | ______| / | | | | | |_____/ | ___|_____|_____|_____|___ | | Qd Qc Qb Qa |-----+---- P=T=1 | CLK-------o|> |_____| | ____| 74x163 | | Carry | |o-------------------+ | Dd Dc Db Da |o---- LD |________________________| | | | | | | | | Now we force a clear whenever the count reaches 1011, so the counter counts the sequence: 0,1,2,3,4,5,6,7,8,9,10,11,0,1,2,3 How would we design a counter that counts from 0 to 11, one that counts from 10 to 15, and one that counts from 4 to 9? Some counters have asynchronous clear or laod inputs (i.e. they don't wait until the next clock edge to act), others are synchronous only (so they wait for the appropriate clock edge). Two 74x163's can be cascased. This counter can counts from 0 to 255. 2^7 2^6 2^5 2^4 2^3 2^2 2^1 2^0 | | | | | | | | ___|____|____|____|____ ___|____|____|____|____ | Qd Qc Qb Qa | | Qd Qc Qb Qa | | ENP|--1 | ENP|--1 -----|RCO ENT|-------|RC0 ENT|--1 | <|--clk | <|--clk | LD|o--1 | LD|o--1 | CLR|o--1 | CLR|o--1 |______________________| |______________________| | | | | | | | | | | | | | | | | Dd Dc Db Da Dd Dc Db Da ENT and ENP are not interchangeable. Only ENT goes to the RCO. The figure below shows 74x163 configured as a free-running counter. _________ | 74x163 | | | CLK----------|> | | | 1-----o|CLR | 1-----o|LD | 1------|ENP | 1------|ENT | | | | | +-------|A Qa|----- 1/2 CLK freq | +-----|B Qb|----- 1/4 CLK freq | | +---|C Qc|----- 1/8 CLK freq | | | +-|D Qd|----- 1/16 CLK freq | | | | | RCO|----- GND----+-+-+-+ |________| (logic 0) Useful as a divide-by-2 -4 -8 or -16 counter. In this mode, Qa will have one half the frequency of the CLK (i.e. it is 0 for two clock cycles and 1 for two clock cycles). Qb will have 1/4 the frequency of the CLK (or 1/2 of Qa) and so on. Similary Qc is 1/8 of the CLK and Qd is 1/16 of CLK. The 74x169 is an up/down binary counter. The state of the UP/DOWN input line determines if the counter counts up or down. State Machines Using Counters (such as the 74x163) A. Use counter for timing B. Implement state machine using the timer 1. Start from a state table/diagram (after state reduction if any) 2. It is easiest to do a straight binary state assignment 3. Reach the reset (assigned to state 0) when the Clear input to the counter is asserted. 4. Counting function is used when a transition to the next state is required (S3-S4) 5. When the next state breaks the normal count sequence (S1-S6) the next state is loaded by asserting LD 6. When the next state loops back to the present state, disable the count (but don't assert LD or CLR)